/*#define CPU_BF537    37

#define BOARD_NAME          "SRV-1 Blackfin Camera Board"
#define CPU                 CPU_BF537*/
#define MASTER_CLOCK        22118000
#define SCLK_DIVIDER        4
#define VCO_MULTIPLIER      22
#define CCLK_DIVIDER        1

#define SDRAM_RECONFIG      1
#define CORE_CLOCK (MASTER_CLOCK * VCO_MULTIPLIER / CCLK_DIVIDER)
#define PERIPHERAL_CLOCK  (CORE_CLOCK / SCLK_DIVIDER)

// UART config

//#define UART0_BAUDRATE 921600
#define UART0_BAUDRATE 57600
#define UART1_BAUDRATE 9600

// must be power of 2!
#define FIFO_LENGTH  64
#define FIFO_MODULO_MASK (FIFO_LENGTH - 1)

#define UART0_DIVIDER   (MASTER_CLOCK * VCO_MULTIPLIER / SCLK_DIVIDER \
                        / 16 / UART0_BAUDRATE)
#define UART1_DIVIDER   (MASTER_CLOCK * VCO_MULTIPLIER / SCLK_DIVIDER \
                        / 16 / UART1_BAUDRATE)
// Blackfin environment memory map

#define L1_DATA_SRAM_A 0xff800000
#define FIFOLENGTH 0x100
